Ethernet Port USRP National Instruments SDR N321

Ethernet port series USRP-LW N321

Product overview
The USRP-LW N321 is a networked software-defined radio that provides reliability and fault tolerance for deployment in large-scale and distributed wireless systems. This is a high-performance SDR that uses a unique RF design that delivers 2 RXs and 2 in a half-width RU size TX channel. Each channel provides up to 200 MHz of instantaneous bandwidth and covers an extended frequency range from 3 MHz to 6 GHz. The baseband processor uses the Xilinx Zynq-7100 SoC to deliver large user-programmable FPGAs for real-time, low-latency processing, as well as dual-core ARM CPUs for stand-alone operation. It has two SPF+ ports and 1 QSFP+ port, and supports 1 GbE, 10 GbE, and Aurora interface that delivers high-throughput IQ streams to a host PC or FPGA coprocessor.


The flexible synchronization architecture supports 10 MHz clock reference, PPS time reference, external TX and RX LO inputs, and GPSDO for phase-coherent MIMO Test platform. The USRP-LW N321 has the ability to import TX and RX LO above 450 MHz support frequencies, making it suitable for building large, phase-coherent topics suitable for a variety of advanced wireless research topics The MIMO test platform provides a path. In addition, the USRP-LW N321 allows the TX and RX LO in the Star configuration to be exported to multiple other USRP-LW N321 devices.
The USRP-LW N321 leverages UHD's latest software developments to simplify the control and management of multiple devices on the network, with unique remote management tasks such as debugging, updating software, rebooting, resetting to factory status, and monitoring system health.

Main features:

• Reliable and fault-tolerant deployment
• Remote management capabilities
• Standalone (embedded) or host-based (network stream) operations
• Fully integrated and assembled (exchangeable daughter cards are not supported by USRP N321).
• Extended frequency range of 3 MHz to 6 GHz
• Instantaneous bandwidth of up to 200 MHz per channel
• 2RX,2TX
• RX, TX filter banks
• 14-bit ADC, 16-bit DAC
• Master clock rates: 200, 245.76, and 250 MS/s
• Xilinx Zynq-7100 SoC
• Dual-core ARM Cortex-A9 800 MHz CPU
• 1 QSFP+ port
• 2 SFP+ ports (1 Gigabit Ethernet, 10 Gigabit Ethernet, Aurora).
• RJ45(1 GbE)
• Clock reference
• PPS time reference
• External RX LO, TX LO input and output ports
• 1 usb host port type A
• 1 micro-USB port (serial console, JTAG).
• Watchdog timer
• OpenEmbedded Linux
• USRP hardware drivers (UHD3.15.0.0 or later) and open source software API versions
• RF Network-on-Chip (RFNoC™) FPGA development framework

Technical specifications